1. Field of the Invention
The present invention relates to a digitally controlled oscillator whose oscillation frequency is controlled by a digital signal.
2. Description of the Related Art
Recently, the research and development of a fully digital phase-locked loop (PLL) whose components are all digital has been advanced. In order to realize a fully digital PLL, a digitally controlled oscillator whose oscillation frequency is digitally controlled is needed.
FIG. 1A shows an example of a conventional digitally controlled oscillator (for example, see Patent reference 1). This digitally controlled oscillator comprises a ring oscillator composed of m inverter circuits 11-1˜11-m. To respective nodes of the ring oscillator, variable load capacitance circuits 12-h (h=1, 2, . . . , m) are connected, and by changing the load capacitance connected to each node by n bits of control signal C[n−1:0], the frequency of the ring oscillator is changed.
Patent reference 1: Japanese Patent Application Publication No. 08-032412
FIG. 1B shows an example of the configuration of the variable load capacitance circuit 12-h shown in FIG. 1A. This variable load capacitance circuit comprises n N-channel metal-oxide semiconductor (NMOS) transistors 13-1˜13-n and n capacitors 14-1˜14-n. Each transistor 13-g (g=1, 2, . . . , n) performs a switching operation by a control signal C[g−1]. If C[g−1] is logic “1” (high), the transistor 13-g connects the capacitor 14-g to CIN. If C[g−1] is logic “0” (low), it disconnects the capacitor 14-g from CIN. Thus, the load capacitance connected to each node of the ring oscillator is changed.
The above-described conventional digitally controlled oscillator has the following problems.
When the capacitance-control type digitally controlled oscillator shown in FIG. 1B is actually built and used in a PLL, a control signal C[n−1:0] always changes, based on information about the phase comparison between a feedback clock signal and a reference clock signal of the PLL.
For example, it is assumed that each of capacitors cap2, cap1 and capo whose capacitance ratio is 4:2:1 are controlled by a control signal xyz. In this case, if, as shown FIG. 1C, capacitance contribution from cap2 changes earlier than that of cap1 or cap0 changes when the end of xyz is carried from “011” to “100”, the entire capacitance instantaneously increases. Conversely, as shown in FIG. 1D, capacitance contribution from cap2 changes later than that of cap1 or cap0 changes, the entire capacitance instantaneously decreases.
When a digital control signal transits in such a way, especially when the on/off of all capacitors is switched where the end of the signal is carried, such a large instantaneous capacitance change gives a timing change (jitter) to the edge of a clock signal generated by a ring oscillator, which is a problem in designing an LSI.